library ieee;

use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.cpu_utils.all;

entity mux_4 is
		generic ( 
		size: integer := 32;
		Tpd : Time := unit_delay);
	port (
			in_0, in_1, in_2, in_3 : in bit_vector(size-1 downto 0);
			y : out bit_vector(size-1 downto 0);
			sel : in bit_vector(1 downto 0));
end mux_4;


architecture mux_4_arh of mux_4 is
begin
	with sel select
		y <= in_0 after Tpd when "00",
		in_1 after Tpd when "01", 
		in_2 after Tpd when "10",
		in_3 after Tpd when "11";
end mux_4_arh;